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| ? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80ec6f79 pdf/09005aef80ec6f65 zip burst cellularram_128__1.fm - rev. a 9/04 en 1 ?2003 micron technology, inc. all rights reserved. 8 meg x 16 async/page/burst cellularram memory preliminary ? 128mb burst cellularram tm 1.5 MT45W8MW16BGX features ? single device supports asynchronous, page, and burst operations vcc, vccq voltages 1.7v?1.95v vcc 1.7v?1.95v vccq random access time: 70ns burst mode read and write access 4, 8, 16, or 32 words, or continuous burst burst wrap or sequential max clock rate: 104 mhz ( t clk = 9.62ns) burst initial latency: 39 ns (4 clocks) @ 104 mhz t aclk: 7ns @ 104 mhz page mode read access sixteen-word page size interpage read access: 70ns intrapage read access: 20ns low power consumption asynchronous read: < 30ma intrapage read: < 15ma initial access, burst read: (39ns [4 clocks] @ 104 mhz) < 40ma continuous burst read: < 25ma standby: < 40a (typ at 25 c) deep power-down: < 3a (typ) low-power features on-chip temperature compensated refresh (tcr) partial array refresh (par) deep power-down (dpd) mode figure 1: ball assignment 54-ball vfbga part number example: MT45W8MW16BGX-701lwt options designator configuration: mt45 w 8mw16 b 8 meg x 16 v cc core voltage supply: 1.8v v cc q i/o voltage supply: 1.8v package 54-ball vfbga??green? gx timing 70ns access -70 85ns access -85 options (continued) designator frequency 66 mhz 6 80 mhz 8 104 mhz 1 standby power at 85c standard: 200a (max) none low-power: 160a (max) l operating temperature range wireless (-30c to +85c) wt industrial (-40c to +85c) it a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 a19 a8 clk a0 a3 a5 a17 a21 a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 rfu cre dq0 dq2 v cc v ss dq6 dq7 a20 rfu a1 a4 a6 a7 a16 a15 a13 a10 a22
8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128toc.fm - rev. a 9/04 en 2 ?2003 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 part-numbering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 partial array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 software access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 burst wrap (bcr[3]) default = no wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 drive strength (bcr[5:4]) default = outputs use half-drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 wait configuration (bcr[8]) default = wait transitions on e clock before data valid/invalid . . . . . . . . .22 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 latency counter (bcr[13:11]) default = three clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 initial access latency (brc[14]) default = variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 partial array refresh (rcr[2:0] default = full a rray refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 deep power-down (rcr[4]) default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 data sheet designation: preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128lof.fm - rev. a 9/04 en 3 ?2003 micron technology, inc. all rights reserved. list of figures figure 1: ball assignment 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram?8 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: read operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: write operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: page mode read operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 8: burst mode read (4-wor d burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 9: burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 10: wired or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 11: refresh collision during variable -latency read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 12: configuration register write, asynchrono us mode followed by read array operation . . . . . .16 figure 13: configuration register write, synchronous mode followed by read array operation . . . . . . .16 figure 14: register read, asynchronous mode followed by read array operation . . . . . . . . . . . . . . . . . . . .17 figure 15: register read, synchronous mode followed by read array operation . . . . . . . . . . . . . . . . . . . . .18 figure 16: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 17: read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 18: bus configuration register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 19: wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 20: wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 21: wait configuration during burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 22: latency counter (variable initial latency, no refresh collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 23: latency counter (fixed latency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 24: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 25: typical refresh current vs. temperature (i tcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 26: ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 27: ac output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 28: initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 29: asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 30: asynchronous read using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 31: page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 32: single-access burst read operation?variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 33: 4-word burst read operation?variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 34: single-access burst read operation?fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 35: 4-word burst read operation?fixe d latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 36: 4-word burst read operation (wit h lb#/ub#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 37: read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 38: continuous burst read showing an output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 39: ce#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 40: lb#/ub#-controlled asyn chronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 41: we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 42: asynchronous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 43: burst write operation? variable latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 44: burst write operation?fixed late ncy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 45: continuous burst write showing an output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 46: burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 47: burst read interrupted by burst read or write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 48: burst write interrupted by burst write or read?v ariable latency mode . . . . . . . . . . . . . . . . . .55 figure 49: burst write interrupted by burst write or read?fix ed latency mode . . . . . . . . . . . . . . . . . . . . .56 figure 50: asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 51: asynchronous write (adv# low) followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 52: burst read followed by asynchro nous write (we#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 53: burst read followed by asynchro nous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 54: asynchronous write followed by asynchronous read ?adv# low . . . . . . . . . . . . . . . . . . . . . . . .61 figure 55: asynchronous write followed by asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 56: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128lot.fm - rev. a 9/04 en 4 ?2003 micron technology, inc. all rights reserved. list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 2: bus operations?asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: bus operations?burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 5: drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6: variable latency configuration code s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7: fixed latency configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 8: 128mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: device identification register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 10: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 11: partial array refresh specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 12: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 13: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 14: asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 15: burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 16: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 17: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 18: initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 19: asynchronous read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 20: asynchronous read timing paramete rs using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 21: asynchronous read timing parameters?page mode operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 22: burst read timing parameters?single access, variable la tency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 9 table 23: burst read timing parameters?4-wor d burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 24: burst read timing parameters?single access, fixed late ncy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 25: burst read timing parameters?4-wor d burst, fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26: burst read timing parameters?4-wor d burst with lb#/ub#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 table 27: burst read timing parameters?burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 28: burst read timing parameters?bcr[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 29: asynchronous write timing parameters?ce#-controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 30: asynchronous write timi ng parameters?lb#/ub#-controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 31: asynchronous write timing parameters?we#-controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8 table 32: asynchronous write timing parameters using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 33: burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 34: burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 35: burst write timing parameters?bcr[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 36: write timing parameters ?burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 37: read timing parameters?burst writ e followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 38: read timing parameters?burst writ e interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 39: write timing parameters?burst write interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 40: write timing parameters?b urst read interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 41: read timing parameters?burst read interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 42: write timing parameters?b urst read interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 43: read timing parameters?burst read interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 44: write timing parameters?async wr ite followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 45: read timing parameters?async write followed by burs t read . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 46: asynchronous write timing parameters?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 47: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 48: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 49: asynchronous write timing parameters?we# controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 50: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 51: asynchronous write timing parameters using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128lot.fm - rev. a 9/04 en 5 ?2003 micron technology, inc. all rights reserved. table 52: write timing parameters?adv# low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 53: read timing parameters?adv# low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 54: write timing parameters?async wr ite followed by async read . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 55: read timing parameters?async write followed by asyn c read . . . . . . . . . . . . . . . . . . . . . . . . . . .62 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 6 ?2003 micron technology, inc. all rights reserved. general description micron ? cellularram? products are high-speed, cmos pseudo-static random access memories devel- oped for low-power, portable applications. the MT45W8MW16BGX device has a 128mb dram core, organized as 8 meg x 16 bits. these devices include an industry-standard burst mode flash interface that dramatically increases re ad/write bandwidth com- pared with other low-power sram or pseudo sram offerings. to operate seamlessly on a burst flash bus, cellu- larram products incorporate a transparent self refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write perfor- mance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its coun- terpart on burst mode flash devices. the refresh con- figuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be upda ted anytime during normal operation. special attention has been focused on standby cur- rent consumption during self refresh. cellularram products include three mechanisms to minimize standby current. partial array refresh (par) enables the system to limit refresh to only that part of the dram array that contains essential data. temperature compensated refresh (tcr) uses an on-chip sensor to adjust the refresh rate to match the device tempera- ture?the refresh rate decreases at lower temperatures to minimize current consumption during standby. deep power-down (dpd) enables the system to halt the refresh operation altogether when no vital infor- mation is stored in the device. the system config- urable refresh mechanisms are accessed through the rcr. this cellularram device is compliant with the industry-standard cellularram 1.5 feature set estab- lished by the cellularram workgroup. it includes sup- port for both variable and fixed latency, with three output-device drive-strength settings, additional wrap options, and a device id register (didr). figure 2: functional bl ock diagram?8 meg x 16 note: functional block diagrams illustrate simplified device operation. see ball descriptions (table 1); bus operations tables (tables 2 and 3); and timing di agrams for detailed information. a[22:0] input/ output mux and buffers control logic 8,192k x 16 dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] address decode logic refresh configuration register (rcr) device id register (didr) bus configuration register (bcr) 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 7 ?2003 micron technology, inc. all rights reserved. l note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchronous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. table 1: vfbga ball descriptions vfbga assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6, e3, j4 a[22:0] input address inputs: inputs for addresses during read and write operations. addresses are internally la tched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. j2 clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static low during asynchronous access read and write operations and during page read access operations. j3 adv# input address valid: indicates that a valid ad dress is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. a6 cre input control register enable: when cre is hi gh, write operations load the rcr or bcr, and read operations access the rcr, bcr, or didr. b5 ce# input chip enable: activate s the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. a2 oe# input output enable: enables the output buff ers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. j1 wait output wait: provides data-valid feedback duri ng burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay asso ciated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. wait is hi gh-z when ce# is high. j5, j6 rfu ? reserved for future use. d6 v cc supply device power supply: (1.70v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.70v?1.95v) powe r supply for inpu t/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 8 ?2003 micron technology, inc. all rights reserved. note: 1. clk must be low during async read and async write modes; and to achieve standby power during standby and dpd modes. clk must be static (hi gh or low) duri ng burst suspend. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb# is in select mode, dq[7:0] are affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will cons ume active power in this mode whenever addresses are changed. 5. when the device is in standby mo de, address inputs and data inputs/outp uts are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (uns witched) in order to achieve standby current. 7. dpd is initiated when ce# transitions fr om low to high after writing rcr[4] to 0. dpd is maintained until ce# transi- tions from high to low. 8. burst mode operation is initialized throug h the bus configuration register (bcr[15]). 9. initial cycle. following cycles are th e same as burst continue. ce# must stay low for the equivalent of a single-word burst (as indicated by wait). table 2: bus operations?asynchronous mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes read active l l l l h l l low-z data-out 4 write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 configuration register write active l l lhlhxlow-zhigh-z configuration register read active l l l l h h l low-z config. reg. out dpd deep power-down l xhxxxxhigh-zhigh-z 7 table 3: bus operations?burst mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes async read active l l l l h l l low-z data-out 4 async write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle lxlxxlxlow-zx 4, 6 initial burst read active l l x h l l low-z data-out 4, 8 initial burst write active l l h l l x low-z data-in 4, 8 burst continue active h l x x x l low-z data-in or data-out 4, 8 burst suspend active x x l h x x x low-z high-z 4, 8 configuration register write active l l h l h x low-z high-z 8, 9 configuration register read active l l l h h l low-z config. reg. out 8, 9 dpd deep power-down l x h x x x x high-z high-z 7 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 9 ?2003 micron technology, inc. all rights reserved. part-numbering information micron cellularram devices are available in several different configurations and densities (see figure 3). figure 3: part number chart valid part number combinations after building the part number from the part num- bering chart above, please go to the micron part mark- ing decoder web site at http://www.micron.com/ partsearch to verify that the part number is offered and valid. if the device required is not on this list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of the device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at http://www.micron.com/partsearch . to view the location of the abbreviated mark on the device, please refer to customer service note, csn-11, ?product mark/label,? at http://www.micron.com/ csn . mt 45 w 8m w 16 b gx -70 8 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.70v?1.95v address locations m = megabits operating voltage w = 1.70v?1.95v bus configuration 16 = x16 read/write operation mode b = asynchronous/page/burst package codes gx = "green" vfbga (6 x 9 grid, 0.75mm pitch, 8.0mm x 10.0mm x 1.0mm) 54-ball production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = -30?c to +85?c it = -40? to +85?c standby power options blank = standard l = low power frequency 6 = 66 mhz 8 = 80 mhz 1 = 104 mhz access/cycle time 70 = 70ns 85 = 85ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 10 ?2003 micron technology, inc. all rights reserved. functional description in general, the MT45W8MW16BGX device is a high- density alternative to sram and pseudo sram prod- ucts, popular in low-power, portable applications. MT45W8MW16BGX contains a 134,217,728-bit dram core, organized as 8,388,608 addresses by 16 bits. the device implements the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asyn- chronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor used to launch the power-up initialization pro- cess. initialization will configure the bcr and the rcr with their default settings (see table 18 on page 20 and table 24 on page 26). v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.7v, the device will require 150s to complete its self-initialization process. during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 4: power-up initialization timing bus operating modes the MT45W8MW16BGX cellularram product incorporates a burst mode interface found on flash products targeting low-powe r, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and wr ite transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh con- figuration register (rcr[7]). asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control bus (ce#, oe#, we#, lb#/ ub#). read operations (figure 5) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 6) occur when ce#, we#, and lb#/ ub# are driven low. during asynchronous write operations, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). asynchrono us operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/write operation. during asynchronous operation, the clk input must be held static low. wait will be driven while the device is enabled and its state should be ignored. we# low time must be limited to t cem. figure 5: read op eration (adv# low) note: adv must remain low for page mode operation. figure 6: write op eration (adv# low) vcc vccq device initialization vcc = 1.7v device ready for normal operation t pu > 150s address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time address < t cem 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 11 ?2003 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. any change in addresses a[4] or higher will initiate a new t aa access time. figure 7 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not include comparable page mode functionality. during asynchronous page mode operation, the clk input must be held low. ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enabled by setting rcr[7] to high. adv must be driven low during all page mode read accesses. due to refresh considerations, ce# must not be low longer than t cem. figure 7: page mo de read operation (adv# low) burst mode operation burst mode operations enable high-speed synchro- nous read and write operations. burst operations consist of a multi-clock sequence that must be per- formed in an ordered fashion. after ce# goes low, the address to access is latched on the rising edge of the next clock that adv# is low. during this first clock ris- ing edge, we# indicates whether the operation is going to be a read (we# = high, figure 8 on page 12) or write (we# = low, figure 9 on page 12). the size of a burst can be specified in the bcr either as a fixed length or continuous. fixed-length bursts consist of four, eight, sixteen, or thirty-two words. continuous bursts have the ability to start at a speci- fied address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. the initial latency for read oper- ations can be configured as fixed or variable (write operations always use fixed latency). variable latency allows the cellularram to be configured for minimum latency at high clock frequencies, but the controller must monitor wait to detect any conflict with refresh cycles. fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. the initial latency time and clock speed determine the latency count setting. the boundaries of 128-word rows should not be crossed in fixed latency mode. fixed latency is used when the controller cannot monitor wait. fixed latency also provides improved performance at lower clock fre- quencies. the wait output asserts as soon as ce# goes low, and de-asserts to indicate when data is to be trans- ferred into (or out of ) the memory. wait will again be asserted if the burst crosses a row boundary (variable latency only?do not cross ro w boundaries when using fixed latency). once the cellularram device has restored the previous row's data and accessed the next row, wait will be de-asserted and the burst can con- tinue (see figure 38 on page 45). to access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. bursts are suspended by stopping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait output will continue to be active, and as a result no other devices should directly share the wait connection to the controller. to con- tinue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. the ce# low time is limited by refresh consider- ations. ce# must not stay low longer than t cem. if a burst suspension will cause ce# to remain low for longer than t cem, ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle. data ce# don?t care oe# we# lb#/ub# address add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa < t cem t apa t apa d[0] 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 12 ?2003 micron technology, inc. all rights reserved. figure 8: burst mode read (4-word burst) note: non-default bcr settings for burst mode read (4-word burst): fixed or variable latency; latency code two (three clocks); wait a ctive low; wait asserted during delay. diagram above is representative of variable latency with no refresh collision or fixed-latency access. figure 9: burst mode write (4-word burst) note: non-default bcr settings for burst mode wri te (4-word burst): fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. a[22:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# latency code 2 (3 clocks) clk undefined don?t care read burst identified (we# = high) address valid a[22:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# address valid latency code 2 (3 clocks) clk don?t care write burst identified (we# = low) 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 13 ?2003 micron technology, inc. all rights reserved. mixed-mode operation the device supports a co mbination of synchronous read and asynchronous read and write operations when the bcr is configured for synchronous opera- tion. the asynchronous read and write operations require that the clock (clk) remain low during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# can remain low when transitioning between mixed-mode operations with fixed latency enabled; however, the ce# low time must not exceed t cem. mixed-mode operation facili- tates a seamless interface to legacy burst mode flash memory controllers. see figure 50 on page 57 for the ?asynchronous write followed by burst read? tim- ing diagram. wait operation the wait output on a cellularram device is typi- cally connected to a shared, system-level wait signal (see figure 10). the shared wait signal is used by the processor to coordinate tr ansactions with multiple memories on the synchronous bus. figure 10: wired or wait configuration once a read or write operation has been initi- ated, wait goes active to indicate that the cellular- ram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to the memory controller when data will be accepted into the cellu- larram device. when wait transitions to an inactive state, the data burst will progress on successive clock edges. ce# must remain asserted during wait cycles (wait asserted and wait configuration bcr[8] = 1). bringing ce# high during wait cycles may cause data corruption. (note that for bcr[8] = 0, the actual wait cycles end one cycle after wait de-asserts, and for row boundary crossings, start one cycle after the wait signal asserts.) when using variable initial access latency (bcr[14] = 0), the wait output perfor ms an arbitration role for read operations launched while an on-chip refresh is in progress. if a collision occurs, wait is asserted for additional clock cycles until the refresh has completed (see figures 11 on page 14). when the refresh operation has completed, the read op eration will continue nor- mally. wait is also asserted when a continuous read or write burst crosses the boundary between 128-word rows. the wait assertion allows time for the new row to be accessed, and permits any pending refresh oper- ations to be performed. wait will be asserted but should be ignored during asynchronous read and write, and page read operations. by using fixed initial latency (bcr[14] = 1), this cel- lularram device can be used in burst mode without monitoring the wait signal. however, wait can still be used to determine when valid data is available at the start of the burst and at row-boundary crossings. if wait is not monitored, the controller must stop burst accesses at row boundaries and restart the burst to access the next row. lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operat ion. during write opera- tions, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as ce# remains low. cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 14 ?2003 micron technology, inc. all rights reserved. figure 11: refresh collision during variable-latency read operation note: non-default bcr settings for refresh col lision during variable-latency read operat ion: latency code two (three clocks); wait active low; wait asserted during delay. a[22:0] adv# ce# oe# we# wait dq[15:0] clk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d[2] d[1] d[3] valid address additional wait states inserted to allow refresh completion. lb#/ub# undefined don?t care d[0] high-z 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 15 ?2003 micron technology, inc. all rights reserved. low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write operation, or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) allows for adequate refresh at different temperatures. this cellular- ram device includes an on-c hip temperature sensor that automatically adjusts the refr esh rate according to the operating temperature. the device continually adjusts the refresh rate to match that temperature. partial array refresh partial array refresh (par) restricts refresh opera- tion to a portion of the total memory array. this fea- ture enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see table 8 on page 27). read and write opera- tions to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. when re-enabling additional portions of the array, the new portions are available immediately upon writing to the rcr. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled by rewriting the rcr, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. dur- ing this 150s period, the current consumption will be higher than the specified standby levels, but consider- ably lower than the active current specification. dpd can be enabled by writing to the rcr using cre or the software access sequence; dpd starts when ce# goes high. dpd is disabled the next time ce# goes low. registers two user-accessible configuration registers define the device operation. the bus configuration register (bcr) defines how the cellularram interacts with the system memory bus and is ne arly identical to its coun- terpart on burst mode flash devices. the refresh config- uration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. a didr provides information on the device manu- facturer, cellularram generation, and the specific device configuration. the didr is read-only. access using cre the registers can be accessed using either a syn- chronous or an asynchronous operation when the control register enable (cre) input is high (see fig- ures 12 through 15 on pages 16 through 18). when cre is low, a read or write operation will access the memory array. the configuration register values are written via addresses a[22:0]. in an asynchronous write, the values are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? the bcr is accessed when a[19:18] are 10b; the rcr is accessed when a[19:18] are 00b. the didr is read when a[19:18] are 01b. for reads, address inputs other than a[19:18] are ?don?t care,? and register bits 15:0 are output on dq[15:0]. 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 16 ?2003 micron technology, inc. all rights reserved. figure 12: configuration regi ster write, asynchronous mode followed by read array operation note: 1. a[19:18] = 00b to load rcr, and 10b to load bcr. figure 13: configuration regi ster write, synchronous mode followed by read array operation note: 1. non-default bcr settings for synchronous mode configuration register write followed by read array operation: latency code two (three clocks); wait active low; wait asserted during delay. 2. a[19:18] = 00b to load rcr, and 10b to load bcr. 3. ce# must remain low to complete a bu rst-of-one write. wait must be monitored? additional wait cycles caused by refresh collisions require a corresponding number of additional ce# low cycles. a[22:0] (except a[19:18]) opcode address address data valid a[19:18] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate control register access write address bus value to control register cre t avs t avh t avh t avs t vp t vph t cbph t wp t cw don?t care select control register clk a[22:0] (except a[19:18]) a[19:18] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t csp t sp t hd high-z don?t care opcode address high-z t cew latch control register value latch control register address t cbph 3 data valid address 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 17 ?2003 micron technology, inc. all rights reserved. figure 14: register read, asynchronous mode followed by read array operation note: a[19:18] = 00b to read rcr, 10b to read bcr, and 01b to read didr. a[22:0] (except a[19:18]) address address data valid cr valid a[19:18] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate register access cre t avh t avs t aa t vp t vph t cbph t co t olz t ba t lz t oe t lz undefined don?t care select register t aavd t avs t aa t hz t ohz t bhz t avh 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 18 ?2003 micron technology, inc. all rights reserved. figure 15: register read, synchronous mode followed by read array operation note: 1. non-default bcr settings for synchronous mode register re ad followed by read array op eration: latency code two (three clocks); wait active low; wait asserted during delay. 2. a[19:18] = 00b to read rcr, 10b to read bcr, and 01b to read didr. 3. ce# must remain low to complete a bu rst-of-one write. wait must be monito red?additional wait cycles caused by refresh collisions require a corresponding number of addition al ce# low cycles. clk a[22:0] (except a[19:18]) a[19:18] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t hz t csp t koh undefined don?t care t sp t hd address t cw latch control register value t olz latch control register address t cbph 3 t boe data valid address t aclk t ohz high-z high-z t aba cr valid 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 19 ?2003 micron technology, inc. all rights reserved. software access software access of the registers uses a sequence of asynchronous read and asynchronous write opera- tions. the contents of the configuration registers can be modified and all registers can be read using the software sequence. the configuration registers are loaded using a four- step sequence consisting of two asynchronous read operations followed by two asynchronous write operations (see figure 16). the read sequence is virtu- ally identical except that an asynchronous read is performed during the fourth operation (see figure 17). the address used during all read and write opera- tions is the highest address of the cellularram device being accessed (7fffffh for 128mb); the contents of this address are not changed by using this sequence. the data value presented during the third operation (write) in the sequence defines whether the bcr, rcr, or the didr is to be accessed. if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the sequence will access the bcr; if the data is 0002h, the sequence will access the didr. during the fourth operation, dq[15:0] transfer data in to or out of bits 15?0 of the registers. the use of the software sequence does not affect the ability to perform the standard (cre-controlled) method of loading the configuration registers. how- ever, the software nature of this access mechanism eliminates the need for cre. if the software mecha- nism is used, cre can simply be tied to v ss . the port line often used for cre control purposes is no longer required. figure 16: load configuration register figure 17: read co nfiguration register address (max) address (max) address (max) address (max) xxxxh xxxxh rcr: 0000h bcr: 0001h cr value in a ddress ce# oe# we# lb#/ub# data don't care read read write write address (max) address (max) address (max) address (max) xxxxh xxxxh cr value out address ce# oe# we# lb#/ub# data don't care read read write read rcr: 0000h bcr: 0001h didr: 0002h 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 20 ?2003 micron technology, inc. all rights reserved. bus configuration register the bcr defines how the cellularram device inter- acts with the system memory bus. page mode opera- tion is enabled by a bit contained in the rcr. figure 18 describes the control bits in the bcr. at power-up, the bcr is set to 9d1fh. the bcr is accessed with cre high and a[19:18] = 10b, or through the register access software sequence with dq = 0001h on the third cycle. figure 18: bus configura tion register definition note: 1. burst wrap and length apply to both read and write operations . a13 13 12 11 0 latency counter initial latency 3 2 1 wait polarity 4 5 wait configuration (wc) 6 7 8 drive strength burst wrap (bw)* 14 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 operating mode synchronous burst access mode asynchronous access mode (default) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4 code 5 code 6 code 7?reserved 0 1 wait polarity active low active high (default) bcr[10] 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) drive strength full 1/2 (default) 1/4 reserved bcr[5] 0 0 1 1 bcr[4] 0 1 0 1 0 1 initial access latency variable (default) fixed bcr[14] burst wrap (note 1) burst wraps within the burst length burst no wrap (default) bcr[3] bcr[1] bcr[0] burst length (note 1) bcr[2] 15 burst length (bl)* reserved reserved 9 10 operating mode reserved 22?20 a14 a15 a[17:16] 0 1 0 register select select rcr select bcr select didr 19?18 17?16 register select reserved a[19:18] a[22:20] reserved must be set to "0" must be set to "0" must be set to "0" all must be set to "0" bcr[8] bcr[15] bcr[19] 0 0 1 bcr[18] 0 1 0 0 0 1 1 0 1 1 0 1 others 1 0 1 0 1 4 words 8 words 16 words 32 words continuous burst (default) reserved setting is ignored (default to "0") 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 21 ?2003 micron technology, inc. all rights reserved. burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words the device outputs during burst read and write operations. the device supports a burst length of 4, 8, 16, or 32 words. the device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries; the in ternal address wraps to 000000h if the burst goes past the last address. burst wrap (bcr[3]) default = no wrap the burst-wrap option determines if a 4-, 8-, 16-, or 32-word read or write burst wraps within the burst length, or steps through sequ ential addresses. if the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the burst goes past the last address. drive strength (bcr[5:4]) default = outputs use half-drive strength the output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. the reduced-strength options are intended for stacked chip (flash + cellular- ram) environments when there is a dedicated memory bus. the reduced-drive-strength option minimizes the noise generated on the data bus during read opera- tions. full output drive strength should be selected when using a discrete cellularram device in a more heavily loaded data bus en vironment. outputs are con- figured at half-drive strength during testing. see table 5 for additional information. ta b l e 4: sequence and burst length burst wrap starting address 4- word burst length 8-word burst length 16-word burst length 32-word burst length continuous burst bcr[3] wrap (decimal) linear l inear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13-? ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-13-14 15-16-17-18-19-20-21-... ... ... ... 30 30-31-0-...-27-28-29 30-31-32-33-34-... 31 31-0-1-...-28-29-30 31-32-33-34-35-... 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2...--29-30-31 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-...-34-35-36 5-6-7-8-9-10-11? 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-...-35-36-37 6-7-8-9-10-11-12? 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13? ... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-44-45 14-15-16-17-18-19-20-? 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-45-46 15-16-17-18-19-20-21-? ... ... ... 30 30-31-32-...-59-60-61 30-31-32-33-34-35-36-... 31 31-32-33-...-60-61-62 31-32-33-34-35-36-37-... 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 22 ?2003 micron technology, inc. all rights reserved. wait configuration (bcr[8]) default = wait transitions one clock before data valid/invalid the wait configuration bit is used to determine when wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. the memory controller will use the wait signal to coordinate da ta transfer during synchro- nous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immedi- ately after wait transitions to the de-asserted or asserted state, respectively (figures 19 and 21). when a8 = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid (figures 20 and 21). wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. figure 19: wait configuration (bcr[8] = 0) note: data valid/invalid immediately after wait transitions (bcr[8] = 0). see figure 21. figure 20: wait configuration (bcr[8] = 1) note: valid/invalid data delayed for one clock after wait transitions (bcr[8] = 1). see figure 21. figure 21: wait configur ation during burst operation note: non-default bcr setting: wait active low. table 5: drive strength bcr[5] bcr[4] drive strength impedance typ ( ? ) use recommendation 0 0 full 25?30 c l = 30pf to 50pf 01 1/2 (default) 50 c l = 15pf to 30pf 104 mhz at light load 1 0 1/4 100 c l = 15pf or lower 1 1 reserved wait dq[15:0] clk data[0] data[1] data immediatel y valid (or invalid) high-z wait d[15:0] clk data[0] data valid (or invalid) after one clock delay high-z wait wait dq[15:0] clk d[0] bcr[8] = 0 data valid in current cycle. bcr[8] = 1 data valid in next cycle. don?t care d[2] d[3] d[1] 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 23 ?2003 micron technology, inc. all rights reserved. latency counter (bcr[13:11]) default = three clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. for allowable latency codes, see tables 6 and 7 and figures 22 and 23). initial access latency (brc[14]) default = variable variable initial access late ncy outputs data after the number of clocks set by th e latency counter. however, wait must be monitored to detect delays caused by collisions with refresh operations. fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh colli- sions. the latency counter must be configured to match the initial latency and the clock frequency. it is not necessary to monitor wait with fixed initial latency. the burst begins after the number of clock cycles configured by the latency counter. the burst will pause (and wait will be asserted) at the boundary of a 128-word row. (see table 7 and figure 23 on page 25.) operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 24 ?2003 micron technology, inc. all rights reserved. note: 1. latency is the number of clock cycles from the initiation of a burst operation until data appears. data is transferred on the next clock cycle. figure 22: latency counte r (variable initial latency, no refresh collision) table 6: variable latency configuration codes bcr[13:11] latency configuration code latency 1 max input clk frequency (mhz) normal refresh collision -701 -708 -856 010 2 (3 clocks) 2 4 66 (15ns) 54 (18.5ns) 40 (25ns) 011 3 (4 clocks)?default 3 6 104 (9.62ns) 80 ( 12.5ns) 66 (15ns) others reserved ????? a[22:0] adv# dq[15:0] clk code 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output code 3 (default) dq[15:0] don?t care undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid address 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 25 ?2003 micron technology, inc. all rights reserved. note: 1. fixed latency > 80 mhz available only with v cc /v cc q from 1.8v?1.95v. figure 23: latency counter (fixed latency) table 7: fixed latency configuration codes bcr[13:11] latency configuration code latency count (n) max input clk frequency (mhz) -701 -708 -856 010 2 (3 clocks) 2 33 (30ns) 33 (30ns) 20 (50ns) 011 3 (4 clocks)?default 3 52 (19.2ns) 52 ( 19.2ns) 33 (30ns) 100 4 (5 clocks) 4 66 (15ns) 66 (15ns) 40 (25ns) 101 5 (6 clocks) 5 75 (13.3ns) 75 (13.3ns) 52 (19.2ns) 110 6 (7 clocks) 6 104 (9.62ns) 1 80 (12.5ns) 66 (15ns) others reserved ???? a[22:0] adv# dq[15:0] (read) clk valid output valid output valid output valid output valid output don?t care undefined v ih v il v ih v il v ih v il ce# v ih v il v oh v ol t aadv t aa t co t aclk t sp t hd dq[15:0] (write) v oh v ol n-1 cycles cycle n valid input valid input valid input valid input valid input burst identified (adv# = low) valid address 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 26 ?2003 micron technology, inc. all rights reserved. refresh configuration register the refresh configuration register (rcr) defines how the cellularram device performs its transparent self refresh. altering the refresh parameters can dra- matically reduce current consumption during standby mode. page mode control is also embedded into the rcr. figure 24 describes the control bits used in the rcr. at power-up, the rcr is set to 0010h. the rcr is accessed with cre high and a[19:18] = 00b; or through the register access software sequence with dq = 0000h on the third cycle (see ?registers? on page 15.) partial array refresh (rcr[2:0] default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host sys- tem. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see table 8 on page 27). figure 24: refresh configur ation register mapping par a4 a3 a2 a1 a0 read configuration register address bus 4 5 1 2 3 0 6 a5 0 1 deep power-down dpd enable dpd disable (default) rcr[4] a6 all must be set to "0" a[17:8] 17?8 19?18 22?20 register select reserved reserved reserved reserved a[22:20] a[19:18] register select select rcr select bcr select didr rcr[19] all must be set to "0" rcr[1] 0 0 1 1 rcr[0] 0 1 0 1 refresh coverage full array (default) bottom 1/2 array bottom 1/4 array bottom 1/8 array rcr[2] 0 0 0 0 00 1 0 1 1 1 0 1 11 1 none of array top 1/2 array top 1/4 array top 1/8 array dpd must be set to "0" setting is ignored (default 00b) a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] 0 1 0 rcr[18] 0 0 1 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 27 ?2003 micron technology, inc. all rights reserved. deep power-down (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initializati on procedure before normal operations can resume. deep power-down is enabled by setting rcr[4] = 0 and taking ce# high. taking ce# low disables dpd and sets rcr[4] = 1; it is not necessary to write to the rcr to disable dpd. dpd can be enabled using cre or the software sequence to access the rcr. page mode operation (rcr[7]) default = disabled the page mode operation bit determines whether page mode is enabled for asynchronous read opera- tions. in the power-up default state, page mode is dis- abled. device identification register the didr provides information on the device man- ufacturer, cellularram generation, and the specific device configuration. table 9 describes the bit fields in the didr. this register is read-only, and is set to 0343h (see table 9). the didr is accessed with cre high and a[19:18] = 01b, or through the register access software sequence with dq = 0002h on the third cycle. table 8: 128mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?7fffffh 8 meg x 16 128mb 0 0 1 one-half of die 000000h?3fffffh 4 meg x 16 64mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 400000h?7fffffh 4 meg x 16 64mb 1 1 0 one-quarter of die 600000h?7fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 700000h?7fffffh 1 meg x 16 16mb table 9: device identifica tion register mapping bit field didr[15] didr[14:11] didr[10:8] didr[7:5] didr[4:0] field name reserved device version devi ce density cellularram generation vendor id bit setting version bit setting 0b 0000b 1st 011b 010b 00011b 0001b 2nd meaning ? 128mb cellularram 1.5 micron 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 28 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings voltage to any ball except v cc , v cc q relative to v ss 0.50v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.2v to +2.45v voltage on v cc q supply relative to v ss -0.2v to +2.45v storage temperature (plastic). . . . . . . . -55oc to +150oc operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -30oc to +85oc industrial . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +85oc soldering temperature and time 10s (solder ball only) . . . . . . . . . . . . . . . . . . . . . +260oc stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. input signals may over shoot to vccq + 1.0v for periods less than 2ns duri ng transitions. 2. input signals may undershoot to vss - 1.0v for period s less than 2ns during transitions. 3. bcr[5:4] = 01b (default setting of one-half drive strength). 4. this parameter is specified with the ou tputs disabled to avoid ex ternal loading effects. th e user must add the current required to drive output capacitanc e expected in the actual system. 5. i sb (max) values measured with par set to full array and at + 85c. in order to achieve low standby current, all inputs must be driven to either v cc q or v ss . i sb might be slightly higher for up to 5 00ms after power-up, or after changes to the par array partition. table 10: electrical characte ristics and operating conditions wireless temperature (-30oc < t c < +85oc); industrial temperature (-40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.7 1.95 v i/o supply voltage v cc q w: 1.8v 1.7 1.95 v input high voltage v ih v cc q - 0.4 v cc q + 0.2 v 1 input low voltage v il -0.20 0.4 v 2 output high voltage i oh = -0.2ma v oh 0.80 v cc qv3 output low voltage i ol = +0.2ma v ol 0.20 v cc qv 3 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current asynchronous random read/ write v in = v cc q or 0v chip enabled, i out = 0 i cc 1-70 30 ma 4 -85 25 asynchronous page read i cc 1p -70 15 ma 4 -85 12 initial access, burst read/write i cc 2 104 mhz 40 ma 4 80 mhz 35 66 mhz 30 continuous burst read i cc 3r 104 mhz 25 ma 4 80 mhz 20 66 mhz 18 continuous burst write i cc 3w 104 mhz 40 ma 4 80 mhz 35 66 mhz 30 standby current v in = v cc q or 0v ce# = v cc q i sb standard 200 a 5 low-power (l) 160 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 29 ?2003 micron technology, inc. all rights reserved. note: i par (max) values measured at 85c. i par might be slightly higher for up to 500ms after changes to the par array parti- tion. figure 25: typical refres h current vs. temperature (i tcr ) note: typical (typ) i zz value applies across all operat ing temperatures and voltages. table 11: partial array refresh specifications and conditions description conditions symbol array partition max units partial array refresh standby current v in = v cc q or 0v, ce# = v cc q i par standard power (no desig.) full 200 a 1/2 170 1/4 155 1/8 150 0140 low-power option (l) full 160 a 1/2 130 1/4 115 1/8 110 0100 120 110 100 90 80 70 60 50 40 30 20 10 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 par = full array par = 1/2 of array par = 1/4 of array par = 1/8 of array par = none of array temperature (?c) current (a) table 12: deep power-down specifications description conditions symbol typ max units deep power-down v in = v cc q or 0v; v cc , v cc q = 1.95v; +85c i zz 325a 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 30 ?2003 micron technology, inc. all rights reserved. note: 1. these parameters are verified in device characterization and are not 100% tested. figure 26: ac input/outp ut reference waveform note: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc q/2. 3. output timing ends at v cc q/2. figure 27: ac outp ut load circuit note: all tests are performed with the output s configured for default setting of ha lf drive strength (bcr[5:4] = 01b). table 13: capacitance description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6 pf 1 input/output capacitance (dq) c io 3.5 6 pf 1 output test points input 1 v cc q v ss v cc q/2 3 v cc q /2 2 dut vccq/2 30pf test point 50 ? 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 31 ?2003 micron technology, inc. all rights reserved. note: 1. low-z to high-z timings are tested wi th the circuit shown in fi gure 27 on page 30. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 2. high-z to low-z timings are tested wi th the circuit shown in figure 27 on pa ge 30. the low-z timi ngs measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 3. page mode en abled only. table 14: asynchronous read cycle timing requirements all tests are performed with the output s configured for default setting of ha lf drive strength (bcr[5:4] = 01b). parameter symbol -701/708 -856 units notes min max min max address access time t aa 70 85 ns adv# access time t aadv 70 85 ns page access time t apa 20 25 ns address hold from adv# high t avh 22ns address setup to adv# high t avs 55ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to dq high-z output t bhz 88ns1 lb#/ub# enable to low-z output t blz 10 10 ns 2 maximum ce# pulse width t cem 44s3 ce# low to wait valid t cew 17.517.5ns chip select access time t co 70 85 ns ce# low to adv# high t cvs 77ns chip disable to dq and wait high-z output t hz 88ns1 chip enable to low-z output t lz 10 10 ns 2 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to dq high-z output t ohz 88ns1 output enable to low-z output t olz 33ns2 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns adv# pulse width low t vp 57ns adv# pulse width high t vph 10 10 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 32 ?2003 micron technology, inc. all rights reserved. note: 1. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfi ed by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 2. low-z to high-z timings are tested wi th the circuit shown in fi gure 27 on page 30. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested wi th the circuit shown in figure 27 on pa ge 30. the low-z timi ngs measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 15: burst read cy cle timing requirements all tests are performed with the output s configured for default setting of ha lf drive strength (bcr[5:4] = 01b). parameter symbol -701 -708 -856 units notes min max min max min max address access time (fixed latency) t aa 70 70 85 ns adv# access time (fixed latency) t aadv 70 70 85 ns burst to read access time (variable latency) t aba 35 46 55 ns clk to output delay t aclk 7911ns address hold from adv# high (fixed latency) t avh 222 ns burst oe# low to output delay t boe 20 20 20 ns ce# high between subsequent burst or mixed- mode operations t cbph 5 6 8 ns 1 maximum ce# pulse width t cem 444s1 ce# low to wait valid t cew 17.517.517.5 ns clk period t clk 9.62 12.5 15 ns chip select access time (fixed latency) t co 70 70 85 ns ce# setup time to active clk edge t csp 345 ns hold time from active clk edge t hd 222 ns chip disable to dq and wait high-z output t hz 8 8 8 ns 2 clk rise or fall time t khkl 1.6 1.8 2.0 ns clk to wait valid t khtl 7911ns clk to dq high-z output t khz 383838 ns clk to low-z output t klz 252525 ns output hold from clk t koh 2 2 2 ns clk high or low time t kp 3 4 5 ns output disable to dq high-z output t ohz 8 8 8 ns 2 output enable to low-z output t olz 333 ns 3 setup time to active clk edge t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 33 ?2003 micron technology, inc. all rights reserved. note: 1. low-z to high-z timings are tested wi th the circuit shown in fi gure 27 on page 30. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 2. high-z to low-z timings are tested wi th the circuit shown in figure 27 on pa ge 30. the low-z timi ngs measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 3. we# low time must be limited to t cem (4s). table 16: asynchronous write cycle timing requirements parameter symbol -701/708 -856 units notes min max min max address and adv# low setup time t as 00ns address hold from adv# going high t avh 22ns address setup to adv# going high t avs 55ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns ce# low to wait valid t cew 1 7.5 1 7.5 ns ce# high between subsequent async operations t cph 55ns ce# low to adv# high t cvs 77ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 20 20 ns chip disable to wait high-z output t hz 88ns1 chip enable to low-z output t lz 10 10 ns 2 end write to low-z output t ow 55ns 2 adv# pulse width t vp 57ns adv# pulse width high t vph 10 10 ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to dq high-z output t whz 88ns 1 write pulse width t wp 45 55 ns 3 write pulse width high t wph 10 10 ns write recovery time t wr 00ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 34 ?2003 micron technology, inc. all rights reserved. note: 1. t as required if t csp > 20ns. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfi ed by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 3. low-z to high-z timings are tested wi th the circuit shown in fi gure 27 on page 30. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 17: burst write cycle timing requirements parameter symbol -701 -708 -856 units notes min max min max min max address and adv# low setup time t as 000 ns1 address hold from adv# high (fixed latency) t avh 222 ns ce# high between subsequent burst or mixed- mode operations t cbph 5 6 8 ns 2 maximum ce# pulse width t cem 444s2 ce# low to wait valid t cew 17.517.517.5 ns clock period t clk 9.62 12.5 15 ns ce# setup to clk active edge t csp 345 ns hold time from active clk edge t hd 222 ns chip disable to wait high-z output t hz 888ns3 last clock to adv# low t kadv 466 ns clk rise or fall time t khkl 1.6 1.8 2.0 ns clock to wait valid t khtl 7911ns clk high or low time t kp 345 ns setup time to activate clk edge t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 35 ?2003 micron technology, inc. all rights reserved. timing diagrams figure 28: initialization period t pu vcc, vccq = 1.7v vcc (min) device ready fo r normal operation table 18: initializatio n timing parameters parameter symbol -701/708 -856 units note min max min max initialization period (require d before normal operations) t pu 150 150 s 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 36 ?2003 micron technology, inc. all rights reserved. figure 29: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t rc t co t bhz t ohz t hz t oe t cew valid output high-z undefined don?t care t blz t lz t olz table 19: asynchronous re ad timing parameters symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t aa 70 85 ns t hz 88ns t ba 70 85 ns t lz 10 10 ns t bhz 8 8 ns t oe 20 20 ns t blz 10 10 ns t ohz 8 8 ns t cew 1 7.5 1 7.5 ns t olz 33ns t co 70 85 ns t rc 70 85 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 37 ?2003 micron technology, inc. all rights reserved. figure 30: asynchronous read using adv# a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t vph t aadv t aa t vp t hz t ba high-z high-z t cvs t co t blz t bhz t ohz t hz t lz t oe t olz valid output t avh t avs high-z undefined don?t care t cew v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il table 20: asynchronous read timing parameters using adv# symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t aa 70 85 ns t cvs 77ns t aadv 70 85 ns t hz 88ns t avh 22ns t lz 10 10 ns t avs 55ns t oe 20 20 ns t ba 70 85 ns t ohz 8 8 ns t bhz 8 8 ns t olz 33ns t blz 10 10 ns t vp 57ns t cew 1 7.5 1 7.5 ns t vph 10 10 ns t co 70 85 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 38 ?2003 micron technology, inc. all rights reserved. figure 31: page mode read a[3:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t co t cem t blz t bhz t ohz t hz t lz t oe t olz t cew high-z undefined don?t care a[22:4] valid address valid address valid address valid address t rc valid output t apa t pc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t oh valid output valid output valid output table 21: asynchronous read timing parameters?page mode operation symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t aa 70 85 ns t hz 8 8 ns t apa 20 25 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 8 8 ns t oh 5 5 ns t blz 10 10 ns t ohz 8 8 ns t cem 44s t olz 33ns t cew 1 7.5 1 7.5 ns t pc 20 25 ns t co 70 85 ns t rc 70 85 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 39 ?2003 micron technology, inc. all rights reserved. figure 32: single-access burst re ad operation?variable latency note: non-default bcr settings: latency code two (three clocks ); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba t hd valid output valid address high-z t koh t ohz t sp lb#/ub# v ih v il t csp t cem high-z t olz t hd t hd t sp t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe high-z table 22: burst read ti ming parameters?single access, variable latency symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aba 35 46 55 ns t hz 8 8 8 ns t aclk 79 11ns t khkl 1.6 1.8 2.0 ns t boe 20 20 20 ns t khtl 7911ns t cem 444s t koh 2 2 2 ns t cew 17.517.517.5ns t kp 345ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t olz 333ns t hd 222ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 40 ?2003 micron technology, inc. all rights reserved. figure 33: 4-word burst read operation?variable latency note: non-default bcr settings: latency code two (three clocks ); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t khkl t hd t aba valid address high-z t koh t hz t hd t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz t hd t kp t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe table 23: burst read timing parameters?4-word burst symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aba 35 46 55 ns t hz 8 8 8 ns t aclk 7911ns t khkl 1.6 1.8 2.0 ns t boe 20 20 20 ns t khtl 7911ns t cbph 5 6 8 ns t koh 2 2 2 ns t cem 444s t kp 345ns t cew 17.517.517.5ns t ohz 8 8 8 ns t clk 9.62 12.5 15 ns t olz 333ns t csp 345ns t sp 3 3 3 ns t hd 222ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 41 ?2003 micron technology, inc. all rights reserved. figure 34: single-access burst read operation?fixed latency note: non-default bcr settings: fixed latency; latency code four (f ive clocks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t clk t cew t avh t co t aadv t aa t hd valid output valid address high-z t koh t ohz t sp t sp lb#/ub# v ih v il t csp t cem high-z t olz t hd t hd t sp t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe high-z table 24: burst read timing para meters?single access, fixed latency symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aa 70 70 85 ns t hd 222ns t aadv 70 70 85 ns t hz 8 8 8 ns t avh 222ns t khkl 1.6 1.8 2.0 ns t boe 20 20 20 ns t khtl 7911ns t cem 444s t koh 2 2 2 ns t cew 17.517.517.5ns t kp 345ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t co 70 70 85 ns t olz 333ns t csp 345ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 42 ?2003 micron technology, inc. all rights reserved. figure 35: 4-word burst re ad operation?fixed latency note: non-default bcr settings: fixed latency; latency code two (thr ee clocks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t avh t clk t khkl t co t aadv t aa high-z t koh t hz t hd t sp t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz t hd t kp t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe valid address table 25: burst read timing para meters?4-word burst, fixed latency symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aa 70 70 85 ns t csp 345ns t aadv 70 70 85 ns t hd 222ns t aclk 7911ns t hz 8 8 8 ns t avh 222ns t khkl 1.6 1.8 2.0 ns t boe 20 20 20 ns t khtl 7911ns t cbph 5 6 8 ns t koh 2 2 2 ns t cem 444s t kp 345ns t cew 17.517.517.5ns t ohz 8 8 8 ns t clk 9.62 12.5 15 ns t olz 333ns t co 70 70 85 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 43 ?2003 micron technology, inc. all rights reserved. figure 36: 4-word burst re ad operation (with lb#/ub#) note: non-default bcr settings: fixed or variab le latency; latency code two (three cl ocks); wait active low; wait asserted during delay; burst length four. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t hd high-z t koh t khz t khz t klz t hz t hd t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz undefined don?t care read burst identified (we# = high) t cew high-z t aclk t khtl valid output valid output valid output t boe valid address t hd table 26: burst read timing para meters?4-word burst with lb#/ub# symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hz 8 8 8 ns t boe 20 20 20 ns t khtl 7911ns t cbph 5 6 8 ns t khz 383838ns t cem 444s t klz 252525ns t cew 17.517.517.5ns t koh 222ns t clk 9.62 12.5 15 ns t ohz 888ns t csp 345ns t olz 333ns t hd 222ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 44 ?2003 micron technology, inc. all rights reserved. figure 37: read burst suspend note: 1. non-default bcr settings for read burst susp end: fixed or variable late ncy; latency code two (thr ee clocks); wait active low; wait asserted during delay. 2. clk can be stopped low or high, but must be static, with no low-to-high trans itions during burst suspend. 3. oe# can stay low during burst susp end. if oe# is low, dq[15:0] wi ll continue to output valid data. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t hd high-z t olz t aclk lb#/ub# v ih v il t clk t sp t csp t sp t hd t hd t sp t hd t koh valid output valid output undefined don?t care valid address high-z t cbph t cem t hz t ohz valid output valid output valid output valid output t boe t ohz t boe t olz high-z valid address note 3 note 2 table 27: burst read timing parameters?burst suspend symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t hz 8 8 8 ns t cbph 5 6 8 ns t koh 222ns t cem 444s t ohz 8 8 8 ns t clk 9.62 12.5 15 ns t olz 333ns t csp 3 4 5 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 45 ?2003 micron technology, inc. all rights reserved. figure 38: continuous burst read showing an output delay with bcr[8] = 0 for variable latency end-of-row condition note: 1. non-default bcr settings for continuous burst read, bcr[8] = 0: wait active low; wait asserted during delay. do not cross row boundaries with fixed latency. 2. ce# must not remain low longer than t cem. 3. wait asserts for anywhere from lc to 2lc cycles. lc = latency code (bcr[13:11]). t aclk t koh a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t khtl t khtl t clk lb#/ub# v ih v il valid output valid output valid output don?t care valid output note 3 note 2 end of row table 28: burst read timi ng parameters?bcr[8] = 0 symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t khtl 7911ns t clk 9.62 12.5 15 ns t koh 2 2 2 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 46 ?2003 micron technology, inc. all rights reserved. figure 39: ce#-controll ed asynchronous write a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in valid address high-z high-z t wc t cew t hz valid input t aw don?t care t wr t cw t cph t dw dq[15:0] out t whz t bw t lz t dh t as t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il high-z table 29: asynchronous write ti ming parameters?ce#-controlled symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 88ns t cph 55ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 00ns t dw 20 20 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 47 ?2003 micron technology, inc. all rights reserved. figure 40: lb#/ ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t dh t as t wp t wph high-z high-z table 30: asynchronous write ti ming parameters?lb#/ub#-controlled symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 8 8 ns t cw 70 85 ns t wp 45 55 ns t dh 0 0 ns t wph 10 10 ns t dw 20 20 ns t wr 0 0 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 48 ?2003 micron technology, inc. all rights reserved. figure 41: we#-controlle d asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address t wc t cew t hz valid input t aw don?t care t wr t dw dq[15:0] out v oh v ol t whz t bw t cw t lz t wp t dh t ow t as t wph high-z high-z high-z table 31: asynchronous write timing parameters?we#-controlled symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t as 00ns t lz 10 10 ns t aw 70 85 ns t ow 55ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 8 8 ns t cw 70 85 ns t wp 45 55 ns t dh 0 0 ns t wph 10 10 ns t dw 20 20 ns t wr 0 0 ns t hz 88ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 49 ?2003 micron technology, inc. all rights reserved. figure 42: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z high-z t cew t hz valid input t vs don?t care t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t as t wph t as t vph t avh t avs t vp t aw high-z table 32: asynchronous write timing parameters using adv# symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t as 00ns t hz 88ns t avh 22ns t lz 10 10 ns t avs 55ns t ow 55ns t aw 70 85 ns t vp 57ns t bw 70 85 ns t vph 10 10 ns t cew 1 7.5 1 7.5 ns t vs 70 85 ns t cw 70 85 ns t whz 8 8 ns t dh 0 0 ns t wp 45 55 ns t dw 20 20 ns t wph 10 10 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 50 ?2003 micron technology, inc. all rights reserved. figure 43: burst write opera tion?variable latency mode note: 1. non-default bcr settings for burst write operation in vari able latency mode: latency code two (three clocks); wait active low; wait asserted during delay; burst length four; burst wrap enabled. 2. wait asserts for lc cycles for both fixed and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t as 3 t csp d[0] d[3] d[2] d[1] valid address t hd t sp t hd t sp t hd t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t care write burst identified (we# = low) t cbph t kadv t khtl t as 3 t hz t cew t kp t khkl note 2 t cem table 33: burst wri te timing parameters symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t as 000ns t hz 888ns t cbph 5 6 8 ns t kadv 466ns t cem 444s t khkl 1.6 1.8 2.0 ns t cew 17.517.517.5ns t khtl 7911ns t clk 9.62 12.5 15 ns t kp 3 4 5 ns t csp 3 4 5 ns t sp 3 3 3 ns t hd 2 2 2 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 51 ?2003 micron technology, inc. all rights reserved. figure 44: burst write operation?fixe d latency mode note: 1. non-default bcr settings for burst write operation in fi xed latency mode: fixed latenc y; latency code two (three clocks); wait active low; wait asserted duri ng delay; burst length four; burst wrap enabled. 2. wait asserts for lc cycles for both fixed and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t as 3 t csp d[0] d[3] d[2] d[1] valid address t hd t sp t hd t sp t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd t kadv don?t care write burst identified (we# = low) t cbph t khtl t as 3 t hz t cew t kp t khkl note 2 t cem t avh table 34: burst wri te timing parameters symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t as 000ns t hd 2 2 2 ns t avh 222ns t hz 888ns t cbph 5 6 8 ns t kadv 466ns t cem 444s t khkl 1.6 1.8 2.0 ns t cew 17.517.517.5ns t khtl 7911ns t clk 9.62 12.5 15 ns t kp 3 4 5 ns t csp 3 4 5 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 52 ?2003 micron technology, inc. all rights reserved. figure 45: continuous burst write showing an output delay with bcr[8] = 0 for variable latency end-of-row condition note: 1. non-default bcr settings for continuous bu rst write, bcr[8] = 0: wait active low; wait asserted during delay. do not cross row boundaries with fixed latency. 2. ce# must not remain low longer than t cem. 3. wait asserts for anywhere from lc to 2lc cycles. lc = latency code (bcr[13:11]). a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t khtl t khtl t clk t sp t hd end of row valid input valid input valid input valid input don?t care v ih v il lb#/ub# note 3 note 2 table 35: burst write timi ng parameters?bcr[8] = 0 symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t clk 9.62 12.5 15 ns t khtl 7811ns t hd 2 2 2 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 53 ?2003 micron technology, inc. all rights reserved. figure 46: burst write followed by burst read note: 1. non-default bcr settings for burst write followed by burst read: fixed or variable late ncy; latency code two (three clocks); wait active low; wait asserted during delay. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfi ed by either of the following two conditions: a) cl ocked ce# high, or b) c e# high for longer than 15ns. ce# ca n stay low between burst read and burst write operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t sp t hd valid address t csp t ohz t koh t aclk valid output valid output valid output valid output high-z high-z v oh v ol lb#/ub# v ih v il t hd t sp t hd t sp t hd t hd high-z undefined don?t care t boe t cbph high-z t hd t hd t sp t kadv note 2 table 36: write timing parameters?bur st write followed by burst read symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t cbph 5 6 8 ns t hd 222ns t clk 9.62 20 12.5 20 15 20 ns t kadv 466ns t csp 3 20420520ns t sp 3 3 3 ns table 37: read timing parameters?bur st write followed by burst read symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 54 ?2003 micron technology, inc. all rights reserved. figure 47: burst read interrupt ed by burst read or write note: 1. non-default bcr settings for burst read interrupted by bur st read or write: fixed or vari able latency; latency code two (three clocks); wait active low; wa it asserted during delay. all bursts show n for variable latency; no refresh colli- sion. 2. burst interrupt shown on first al lowable clock (i.e., after the fir st data received by controller). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle read v ih v il oe# 2nd cycle write v ih v il we# v ih v il wait dq[15:0] out 2nd cycle read v oh v ol clk v ih v il dq[15:0] in 2nd cycle write v ih v il t hd t sp t sp t hd t clk t ohz t hd t koh t aclk valid output valid output valid output valid output high-z lb#/ub# 2nd cycle read v ih v il lb#/ub# 2nd cycle write v ih v il t sp t hd undefined don?t care high-z t hd t sp t csp t sp t hd valid address t ohz t koh t aclk valid output valid output high-z t boe t sp t hd t hd t sp v oh v ol t boe d[2] d[3] d[1] d[0] high-z t cem ( note 3 ) valid address read burst interrupted with new read or write. see note 2. table 38: read timing paramet ers?burst wri te interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns table 39: write timing parameters?burst write interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t clk 9.62 20 12.5 20 15 20 ns t hd 222 ns t csp 3 20 4 20 5 20 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 55 ?2003 micron technology, inc. all rights reserved. figure 48: burst write interr upted by burst write or read? variable latency mode note: 1. non-default bcr settings for burst write interrupted by burst write or read in variable latency mode: fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. all bursts shown for variable latency; no refresh collision. 2. burst interrupt shown on first allowable clock (i.e., after first data word written). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle write v ih v il oe# 2nd cycle read v ih v il we# v ih v il wait dq[15:0] in 2nd cycle write dq[15:0] out 2nd cycle read v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d[0] valid address t hd t sp t hd t sp t sp t hd valid address t hd high-z lb#/ub# 2nd cycle write lb#/ub# 2nd cycle read v ih v il v ih v il t hd t sp t hd t sp t hd high-z undefined don?t care d[2] d[3] d[1] d[0] t hd t sp high-z t hd t hd t sp t kadv t ohz t boe t koh t aclk valid output valid output valid output valid output high-z v oh v ol v oh v ol write burst interrupted with new write or read. see note 2. valid address t cem ( note 3 ) table 40: write timing paramet ers?burst read interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t clk 9.62 20 12.5 20 15 20 ns t kadv 466 ns t csp 3 20 4 20 5 20 ns t sp 3 3 3 ns t hd 222ns table 41: read timing paramet ers?burst read interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 56 ?2003 micron technology, inc. all rights reserved. figure 49: burst write in terrupted by burst write or read?fixed latency mode note: 1. non-default bcr settings for burst write interrupted by burst write or read in fixed latency mode: fixed latency; latency code two (three clocks); wait active low; wait asserted during delay. 2. burst interrupt shown on first allowable clock (i.e., after first data word written). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle write v ih v il oe# 2nd cycle read v ih v il we# v ih v il wait dq[15:0] in 2nd cycle write dq[15:0] out 2nd cycle read v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d[0] valid address t hd t sp t hd t sp t sp valid address t hd high-z lb#/ub# 2nd cycle write lb#/ub# 2nd cycle read v ih v il v ih v il t sp t hd t sp t hd high-z undefined don?t care d[2] d[3] d[1] d[0] t hd t sp high-z t hd t sp t ohz t boe t koh t aclk valid output valid output valid output valid output high-z v oh v ol v oh v ol write burst interrupted with new write or read. see note 2. valid address t cem ( note 3 ) t kadv t avh t avh t hd table 42: write timing paramet ers?burst read interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t avh 222ns t hd 222ns t clk 9.62 20 12.5 20 15 20 ns t kadv 466ns t csp 3 20420520ns t sp 3 3 3 ns table 43: read timing paramet ers?burst read interrupted symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 57 ?2003 micron technology, inc. all rights reserved. figure 50: asynchronous wri te followed by burst read note: 1. non-default bcr settings for asynchronous write followed by burst read: fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. ce# can stay low when transitioning to fixed-latency burst reads. a refresh opportunity must be provided every t cem. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high , or b) ce# high for longer than 15ns. t clk t sp t hd t sp valid address t ohz t koh t aclk high-z high-z valid address valid address t avs t avh t aw t wr t vp t vs a[22:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t cvs t wph t as t as t wp t wc t dh t dw data data high-z t hd t sp t cew t sp t hd t csp t wc t wc t bw valid output valid output valid output valid output don?t care undefined t hd t boe t cbph t vph note 2 table 44: write timing parameters?asy nc write followed by burst read symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t avh 22ns t dw 20 20 ns t as 00ns t vp 57ns t avs 55ns t vph 10 10 ns t aw 70 85 ns t vs 70 85 ns t bw 70 85 ns t wc 70 85 ns t cvs 77ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns table 45: read timing parameters?asy nc write followed by burst read symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t csp 3 4 5 ns t boe 20 20 20 ns t hd 2 2 2 ns t cbph 5 6 8 ns t koh 2 2 2 ns t cew 1 7.5 1 7.5 1 7.5 ns t ohz 888 ns t clk 9.62 12.5 15 ns t sp 3 3 3 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 58 ?2003 micron technology, inc. all rights reserved. figure 51: asynchronous write (adv# low) foll owed by burst read note: 1. non-default bcr settings for asynchronous write, with adv# lo w, followed by burst read: fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. ce# can stay low when transitioning to fixed-latency burst reads. a refresh opportunity must be provided every t cem. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high , or b) ce# high for longer than 15ns. t clk t sp t hd t hd valid address t csp t koh t aclk valid output high-z valid address valid address a[22:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t wp t wc t dh t dw data data high-z t hd t sp t sp t hd t wc t wc t bw t aw t wr t sp valid output valid output valid output undefined don?t care t boe t ohz t cew t cbph high-z note 2 table 46: asynchronous write timing parameters?adv# low symbol -701/708 -856 units symbol -701/708 -856 units min max min max min max min max t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 0 0 ns t dw 20 20 ns table 47: burst read timing parameters symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 7911ns t csp 345ns t boe 20 20 20 ns t hd 222ns t cbph 5 6 8 ns t koh 2 2 2 ns t cew 17.517.517.5ns t ohz 888 ns t clk 9.62 12.5 15 ns t sp 333ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 59 ?2003 micron technology, inc. all rights reserved. figure 52: burst read followed by asynchronous write (we#-controlled) note: 1. non-default bcr settings for burst read fo llowed by asynchronous we#-controlled write: fixed or variable latency; latency cod e two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go hi gh. ce# can stay low when transi - tioning from fixed-latency burst reads. a refr esh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked c e# high, or b) ce# high for longer than 15ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aw t cw t wr valid output valid address high-z t koh t dw t ohz t sp lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) t wc t hd t khtl t boe valid address valid input high-z t cew t hz t cbph note 2 table 48: burst read timing parameters symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 79 11ns t hd 222ns t boe 20 20 20 ns t hz 8 8 8 ns t cbph 568ns t khtl 7911ns t cew 17.517.517.5ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns table 49: asynchronous write timing parameters?we# controlled symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 0 0 ns t dw 20 20 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 60 ?2003 micron technology, inc. all rights reserved. figure 53: burst read followed by asynchronous write using adv# note: 1. non-default bcr settings for burst read followed by asynchronous write using adv#: fixed or variable latency; latency code tw o (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. ce# can stay low when transi tioning from fixed-latency burst reads. a refres h opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the fol- lowing two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t cew t hd t vph t vs t avs t avh t aw t cw valid output valid address high-z t koh t dw t ohz t sp t hd t vp lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t sp undefined don?t care read burst identified (we# = high) t khtl valid address valid input high-z t cew t hz t cbph t aclk t boe t as t hd note 2 table 50: burst read timing parameters symbol -701 -708 -856 units symbol -701 -708 -856 units min max min max min max min max min max min max t aclk 79 11ns t hd 222ns t boe 20 20 20 ns t hz 8 8 8 ns t cbph 568ns t khtl 7911ns t cew 17.517.517.5ns t koh 2 2 2 ns t clk 9.62 12.5 15 ns t ohz 8 8 8 ns t csp 345ns t sp 333ns table 51: asynchronous write timing parameters using adv# symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t as 00ns t dw 20 20 ns t avh 22ns t hz 88ns t avs 55ns t vp 57ns t aw 70 85 ns t vph 10 10 ns t bw 70 85 ns t vs 70 85 ns t cew 1 7.5 1 7.5 ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 61 ?2003 micron technology, inc. all rights reserved. figure 54: asynchronous write followed by asyn chronous read?adv# low note: 1. when configured for synchronous mode (bcr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the appropriate refresh interval. otherwise, t cph is only required after ce#-controlled writes. valid address valid address a[22:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# v ih v il v ih v il v ih v il v ih v il t cw t wph t wp t as t wc t dh t dw data high-z valid address t aa t bhz t cph valid output high-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw t whz t hz t hz don?t care undefined data note 1 table 52: write timing parameters?adv# low symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88 ns t cph 55ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns t dw 20 20 ns table 53: read timing parameters?adv# low symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t bhz 88 ns t oe 20 20 ns t blz 10 10 ns t ohz 88 ns t hz 88 ns t olz 33ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 62 ?2003 micron technology, inc. all rights reserved. figure 55: asynchronous write followed by asynchronous read note: 1. when configured for synchronous mode (bcr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the appropriate refresh interval. otherwise, t cph is only required after ce#-controlled writes. valid address valid address t avs t avh t vph t vp t vs a[22:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# t cw t wph t as t wp t wc t dh t dw data data high-z valid address t aa t bhz t cph valid output high-z t cvs t olz t lz t as t blz t ohz t hz t aw t wr t bw t whz undefined don?t care t oe note 1 table 54: write timing parameters?asy nc write followed by async read symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t as 00ns t dw 20 20 ns t avh 22ns t vp 57ns t avs 55ns t vph 10 10 ns t aw 70 85 ns t vs 70 85 ns t bw 70 85 ns t wc 70 85 ns t cph 55ns t whz 88ns t cvs 77ns t wp 45 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 00ns table 55: read timing parameters?a sync write followed by async read symbol -701/-708 -856 units symbol -701/-708 -856 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t bhz 88 ns t oe 20 20 ns t blz 10 10 ns t ohz 88 ns t hz 88 ns t olz 33ns 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 63 ?2003 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. figure 56: 54-ball vfbga note: 1. all dimensions in millimeters; max/min, or typical, as noted. data sheet designation: preliminary this data sheet contains initial characterization limits, subject to change upon full characterization of production devices. ball a1 id 1.00 max mold compound: epoxy novolac substrate: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu solder ball pad: ? 0.30 solder mask defined ball a6 ball a1 8.00 0.10 4.00 0.05 1.875 0.05 ball a1 id 54x ? 0.37 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.35 c l c l 0.75 typ 5.00 0.05 3.00 0.05 6.00 10.00 0.10 0.70 0.05 0.10 c c seating plane 3.75 0.75 typ 8 meg x 16 async/page/burst cellularram memory preliminary 09005aef80ec6f79 pdf/09005aef80ec6f65 zip micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram_128__2.fm - rev. a 9/04 en 64 ?2003 micron technology, inc. all rights reserved. revision history rev. a, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04 initial release. |
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